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MOS MOS Integrated Circuit
PD720133
USB2.0-IDE
PD720133
USB2.0
ATA/ATAPI
LSI
Universal Serial Bus
Specification Revision 2.0
High-speed Capable device
USB2.0 ATA/ATAPI
PD720133 CISC Processor, ATA/ATAPI Controller, Endpoint Controller (EPC), Serial Interface
Engine (SIE) Protocol) USB2.0 Transceiver EPC USB2.0 Protocol Class Specific Protocol (Bulk Only V30MZ CISC Processor EEPROM USB2.0 Transceiver SIE Transport Layer ROM
PD720133
Universal Serial Bus Specification Revision 2.0 (Data Rate 12/480 Mbps) ATA/ATAPI-6 (LBA48, PIO Mode 0-4, Multi Word DMA Mode 0-2, Ultra DMA Mode 0-4) "USB2.0 High-speed Bus Powered Device" USB Implementers Forum Full-speed USB 2.0 High-speed Logo (TID: 40001985) USB2.0 High-speed Transceiver / Receiver
USB2.0 High-speed Full-speed Packet Protocol Sequencer (Serial Interface Engine) Chirp Full-/High-speed Mode
set feature (TEST_MODE) CD-ROM, HDD 30 MHz X'tal VDD33 = 3.3 V VDD25 = 2.5 V 2 IDE
PD720133GB-YEU-A 64 PD720133GB-YEU-Y 64
TQFP TQFP
10 10 10 10
S17100JJ2V0DS00 2 June 2004 NS CP (N)
2004
PD720133
CPU Core (V30MZ)
RAM 2 Kbytes x 2 ROM 12 Kbytes
EPC2_V2
PHY_V2
USB Bus
DCC
16-bit Bus
Bus Bridge 16-bit Bus DMAC
IDEC_V2
IDE Bus
GPIO GPIO 8-bit Bus INTC Timer
PIO
Direct Bus Direct Command Bus
Serial ROM
V30MZ RAM ROM PHY_V2 EPC2_V2 IDEC_V2 DCC Bus Bridge INTC GPIO PIO
: CISC CPU core : 4-Kbyte work RAM for firmware : 12-Kbyte ROM for built-in firmware : USB2.0 transceiver with serial interface engine : Endpoint controller : IDE controller : ATA direct command controller : Internal / external bus controller and DMA controller : Interrupt controller (82C59 like) : General purpose 3-bit I/O controller : Multipurpose 2-bit I/O controller
2
S17100JJ2V0DS
PD720133
Top View
64 TQFP 10 10
PD720133GB-YEU-A PD720133GB-YEU-Y
64
56
49 48
SCAN RPU VDD25 VSS RSDP DP VDD33 DM RSDM VSS AVDD25 AVSS RREF AVSS(R) AVDD25 TEST
1
CMB_BSY CMB_STATE DPC SCL SDA RESETB VDD25 VSS XOUT XIN VDD33 IDERSTB IDED7 IDED8 IDED6 VSS
8
41
16 17 25 32
33
IDE9 IDED5 IDED10 IDED4 IDED11 IDED3 IDED12 VDD33 VSS VDD25 IDED2 IDED13 IDED1 IDED14 IDED0 IDED15
VBUS IDECS1B IDECS0B IDEA2 IDEA0 IDEA1 IDEINT VDD33 VSS VDD25 IDEDAKB IDEIORDY IDEIORB IDEIOWB IDEDRQ VSS
S17100JJ2V0DS
3
PD720133
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SCAN RPU VDD25 VSS RSDP DP VDD33 DM RSDM VSS AVDD25 AVSS RREF AVSS(R) AVDD25 TEST
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VBUS IDECS1B IDECS0B IDEA2 IDEA0 IDEA1 IDEINT VDD33 VSS VDD25 IDEDAKB IDEIORDY IDEIORB IDEIOWB IDEDRQ VSS
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
IDED15 IDED0 IDED14 IDED1 IDED13 IDED2 VDD25 VSS VDD33 IDED12 IDED3 IDED11 IDED4 IDED10 IDED5 IDED9
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
VSS IDED6 IDED8 IDED7 IDERSTB VDD33 XIN XOUT VSS VDD25 RESETB SDA (PIO0) SCL (PIO1) DPC(GPIO5) CMB_STATE(GPIO6) CMB_BSY(GPIO7)
AVSS(R)
2.43 k 1%
RREF
4
S17100JJ2V0DS
PD720133
1.
XIN XOUT RESETB IDECS(1:0)B IDEA(2:0) IDEINT
I O I O (I/O) O (I/O) I
2.5 V 2.5 V 3.3 V Schmitt 5 V tolerant 5 V tolerant 5 V tolerant High Low Low IDE IDE IDE
IDEDAKB IDEIORDY IDEIORB IDEIOWB IDEDRQ
O (I/O) I O (I/O) O (I/O) I
5 V tolerant 5 V tolerant 5 V tolerant 5 V tolerant 5 V tolerant
Low High Low Low High
IDE DMA IDE IO IDE IO IDE IO IDE DMA
IDED(15:0) IDERSTB CMB_BSY (GPIO7) CMB_STATE (GPIO6) DPC (GPIO5) SDA (PIO0) SCL (PIO1) VBUS DP DM RSDP RSDM RPU RREF SCAN TEST AVDD25 VDD25 VDD33 AVSS VSS
I/O O (I/O) I/O I/O I/O I/O I/O I I/O I/O O O A A I I
5 V tolerant 5 V tolerant 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 5 V Schmitt USB high speed D+ I/O USB high speed D- I/O USB full speed D+ O USB full speed D- O USB pull-up control Analog 3.3 V 3.3 V Low
IDE IDE IDE IDE IDE ROM ROM VBUS USB high speed D+ USB high speed DUSB full speed D+ USB full speed DUSB 1.5 k
2.5 V VDD 2.5 V VDD 3.3 V VDD
VBUS
VBUS
VDD33, VDD25 VBUS
AVDD25
VSS
3.0 V
1. 2.
"5 V tolerant" "(I/O)"
5V
3.3 V
S17100JJ2V0DS
5
PD720133
2.
USB-IDE
PD720133, USB Vendor ID, Product ID PD720133 PD720133
2 IDE IDE IDE 1 IDE
ROM USB-IDE high-speed capable bus powered system
PD720133
ROM
IDE
PD720133
2.1 ROM
IDE
PD720133 Vendor ID, Product ID USB
ROM
ROM
21
ROM
H +00 +02 +04 +06 +07 +08 +0A +0C +0E +10 1 1 1 1 1 1 1 1 1 1 idMark CheckSum Flags ModeReset ModeSet idVendor idProduct bcdDevice Reserved MaxPower Bus Configuration bMaxPower PWR, CLC, DCC, DV[1:0] , DPC PWR, CLC, DCC, DV[1:0] , DPC Device Device Device idVendor idProduct bcdDevice Validation Mark (Symbol : 55AAH) ROM
+11
1
MaxPower Self
Configuration
bMaxPower
+12 +13 +14 +15 +16 +18 +1A +1C +20 +40 +60 +80
1 1 1 1 1 1 1 4 32 32 32 128 n
bInterfaceClass bInterfaceSubClass bInterfaceProtocol Reserved TxModeReset TxModeSet ROMpatchSW Reserved ManufactureString ProductString SerialString FW Patch
Interface Interface Interface
bInterfaceClass bInterfaceSubClass bInterfaceProtocol
Ultra DMA 66 Ultra DMA 66 ROM
IDE IDE (ROM ON/OFF )
Manufacturer String Product String String
Device Serial Number
6
S17100JJ2V0DS
PD720133
2.2 ROM SCL, SDA ROM TEST, SCAN SCL
22
SCL SDA TEST SCAN
ROM
2K
SCL
CMB_BSY, CMB_STATE IDE CMB_STATE IDE 1 IDE
USB-IDE IDE
2
PD720133
IDE
CMB_BSY
PD720133
CMB_BSY CMB_STATE
S17100JJ2V0DS
7
PD720133
2.3 ROM ROM IDE IDE
2 3 DV1/DV0, CLC, PWR
No. ATA/ATAPI PWR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ATA ATAPI 60 MHz ATA ATAPI 60 MHz ATA ATAPI 7.5 MHz ATA ATAPI 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 CLC 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 ROM DV1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 DV0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
1. 2. 3.
No. 0, 3, 4, 7, 8, 12
Slave
ATA/ATAPI
2 4 DV1/DV0, DCC
ROM DV1 1 DV0 0 ATA ATA DCC Reset Set 0 1 ATAPI ATAPI Reset Set 0 0 ATA Reset Set ATAPI Reset Set Ultra, Multi Word DMA Ultra, Multi Word DMA Ultra DMA OFF ON OFF ON OFF ON
Ultra, Multi Word DMA Ultra, Multi Word DMA Ultra, Multi Word DMA Ultra DMA OFF
Ultra, Multi Word DMA
ON
PIO Mode 0-4
8
S17100JJ2V0DS
PD720133
2.4
PD720133
2 IDE
IDE
1
IDE
2
IDE
PD720133
PWR = 0 CLC = 1
CMB_BSY CMB_STATE CMB_BSY CMB_STATE
2 1 CMB_BSY
CMB_STATE
IDE
PD720133
CMB_STATE CMB_BSY
Other IDE controller IDE Bus Grant IDE Bus Request
2 5 CMB_BSY
CMB_STATE
CMB_STATE
IN
0 1 0 1
IDE IDE
CMB_BSY
OUT
PD720133 IDE PD720133 IDE
S17100JJ2V0DS
9
PD720133
IDE
PD720133
IDE
IDE IDE IDE
IDE
PD720133 PD720133
CMB_STATE
IDE
2 2 IDE
START
Chip Init A B Suspend Mode
PWR = 0 & CLC = 1 ?
Yes END No CMB_STATE = 1 ? A
IDE IDE IDE
Yes
IDE IDE
Yes
IDE
CMB_STATE = 1 ? No No CMB_BSY = 1 B CMB_STATE = 0 ? No CMB_BSY = 0
PD720133IDE
Resume
Yes
PD720133IDE
END
A
10
S17100JJ2V0DS
PD720133
2.5 USB2.0-IDE 7.5 MHz
PD720133 2
60 MHz
PD720133
23 a
Power OFF Vbus OFF
Power OFF
Vbus ON Connect Hardware Reset Idle Mode
Power = PRESET
Bus Reset FS CONNECT
Default State
HS CONNECT
FS Enumeration State
Power = PENUM_FS
Resume Suspend Resume
HS Enumeration State
Set Configuration
Suspend
Power = PENUM_HS
Resume
Set Configuration
Suspend Mode
Suspend Suspend Resume Resume
Suspend Mode
Configured State
Configured State
Suspend
FS Operation State
Power = PSPND
Suspend
HS Operation State
Power = PSPND
Resume
Power = PFS_B
Power = PHS_B
b
Power OFF
Power OFF
Power ON Hardware Reset Idle Mode Power = PRESET CMB_STATE = 0 CMB_STATE = 1 Bus Reset
IDE Bus Release State
Disconnect Mode
Vbus OFF
Vbus ON Connect
Default State
FS CONNECT
HS CONNECT
Power = PCOMBO
FS Enumeration
State
Resume
HS Enumeration State
Power = PENUM_FS
Set Configuration
Suspend Suspend Resume Suspend
Power = PENUM_HS Set Configuration
Suspend Mode Configured State
Resume Suspend Resume
Suspend
Suspend Mode
Configured State
Power = PSPND
Suspend
HS Operation State
Power = PSPND
Resume
FS Operation State
Resume
Power = PFS_S
Power = PHS_S
S17100JJ2V0DS
11
PD720133
USB2.0-IDE
PD720133 PD720133 IDE
IDE DPC
DPC
USB 3.3 V
PD720133
2 4 DPC
IDE
Default
Un-configured
Configured
Suspend
Configured
DPC
ON
Set Configuration
IDE IDE IDE OFF
DPC OFF USB suspend
Configured
25
Power supply rail IDE Device 3.3V
PD720133
Pull-up
IN
OUT
Regulator
Power
P-Channel Switch
DPC
ON
12
S17100JJ2V0DS
PD720133
3.
3.1
* * * * * * *
2.5 V XIN, XOUT 3.3 V SCAN, TEST 3.3 V RESETB 3.3 V IOL = 3 mA OR-type
SDA, SCL, DPC (GPIO5), CMB_STATE (GPIO6), CMB_BSY (GPIO7) 5V VBUS 5 V IOL = 6 mA OR-type
IDED(15:0), IDEINT, IDEIORDY, IDEDRQ, IDECS(1:0)B, IDEA(2:0), IDEDAKB, IDEIORB, IDEIOWB, IDERSTB USB DP, DM, RSDP, RSDM, RREF, RPU 5V 3.3 V 5V 3.3 V 5V
S17100JJ2V0DS
13
PD720133
3.2
VDD33, VDD25 VI VO IO
VDD
DC
TA Tstg
VDD33, VDD25 VIH
VSS = 0 V
LSI
MIN. VIL LSI
MAX. VH tri tfi LSI LSI 10% 90% 90% 10%
DC
IOZ 3
IOS II IOL IOH
GND
14
S17100JJ2V0DS
PD720133
3.3
VDD33 VDD25 ,5V VI
3.3 V 2.5 V 3.0 V VDD33 3.6 V
0.5 0.5 0.5
4.6 3.6 6.6
V V V
VI < VDD33 3.0 V 3.0 V VDD33 3.6 V
, 3.3 V
VI
VI < VDD33 1.0 V 2.3 V VDD25 2.7 V
0.5
4.6
V
, 2.5 V
VI
VI < VDD25 0.9 V 3.0 V VDD33 3.6 V
0.5
3.6
V
,5V
VO
VO < VDD33 3.0 V 3.0 V VDD33 3.6 V
0.5
6.6
V
, 3.3 V
VO
VO < VDD33 1.0 V 2.3 V VDD25 2.7 V
0.5
4.6
V
, 2.5 V ,5V , 3.3 V
VO IO IO TA Tstg
VO < VDD25 0.9 V IOL = 6 mA IOL = 6 mA IOL = 3 mA
0.5 20 20 10 0 65
3.6
V mA mA mA
70 150
1
2
PD720133 2.5 V 3.3 V 2
2 VDD25 VDD25 VI/VO VDD25 VDD33 VDD33
PD720133 VDD33
100 ms
S17100JJ2V0DS
15
PD720133
MIN. VDD33 VDD25 VDD25 VIH 5.0 V 3.3 V 2.5 V VIL 5.0 V 3.3 V 2.5 V VH 5V 3.3 V tri 0 0 tfi 0 0 0.3 0.2 0 0 0 2.0 2.0 1.7 VDD33 VDD25 AVDD25 3.3 V 2.5 V 2.5 V 3.0 2.3 2.3
TYP. 3.3 2.5 2.5
MAX. 3.6 2.7 2.7 V V V
5.5 VDD33 VDD25
V V V
0.8 0.8 0.7
V V V
1.5 1.0
V V
200 10
ns ms
200 10
ns ms
DC
VDD33 = 3.0 3.6 V, VDD25 = 2.3 2.7 V, TA = 0
70
MIN. IOZ IOS IOL 5.0 V 3.3 V 3.3 V IOH 5.0 V 3.3 V 3.3 V II 3.3 V 5.0 V VI = VDD or VSS VI = VDD or VSS VOH = 2.4 V VOH = 2.4 V VOH = 2.4 V 2.0 6.0 3.0 VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V 6.0 6.0 3.0 VO = VDD33, VDD25 or VSS
MAX. 10 250
A
mA
mA mA mA
mA mA mA
10 10
A A
1
LSI
1
16
S17100JJ2V0DS
PD720133
USB
MIN. Serial resistor between DP (DM) and RSDP (RSDM) Output pin impedance Bus pull-up resistor on upstream facing port ZHSDRV RPU Includes RS resistor 1.5 k 5% consists of resistance of transistor and pull-up resistor Termination voltage for upstream facing port pull-up Input Levels for Full-speed: High-level input voltage (drive) High-level input voltage (floating) Low-level input voltage Differential input sensitivity Differential common mode range Output Levels for Full-speed: High-level output voltage Low-level output voltage SE1 Output signal crossover point voltage Input Levels for High-speed: High-speed squelch detection threshold (differential signal) High-speed disconnect detection threshold (differential signal) High-speed data signaling common mode voltage range High-speed differential input signaling level Output Levels for High-speed: High-speed idle state High-speed data signaling high High-speed data signaling low Chirp J level (differential signal) Chirp K level (differential signal) VHSOI VHSOH VHSOL VCHIRPJ VCHIRPK -10.0 360 -10.0 700 -900 +10.0 440 +10.0 1100 -500 mV mV mV mV mV 3-4 VHSCM -50 +500 mV VHSDSC 525 625 mV VHSSQ 100 150 mV VOH VOL VOSE1 VCRS RL of 14.25 k to VSS RL of 1.425 k to 3.6 V 2.8 0.0 0.8 1.3 2.0 3.6 0.3 V V V V VIH VIHZ VIL VDI VCM (D+) - (D-) Includes VDI range 0.2 0.8 2.5 2.0 2.7 3.6 0.8 V V V V VTERM 3.0 3.6 V 40.5 1.485 49.5 1.515 RS 38.61 MAX. 39.39
S17100JJ2V0DS
17
PD720133
3 1 Differential Input Sensitivity Range for Low-/full-speed
Differential Input Voltage Range Differential Output Crossover Voltage Range
-1.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 4.6
Input Voltage Range (V)
3 2 Full-speed Buffer VOH/IOH Characteristics for High-speed Capable Transceiver
VDD-3.3 VDD-2.8 VDD-2.3 VDD-1.8 VDD-1.3 VDD-0.8 VDD-0.3 VDD 0
-20
IOUT (mA)
-40 Min. -60 Max. -80 VOUT (V)
3 3 Full-speed Buffer VOL/IOL Characteristics for High-speed Capable Transceiver
80 Max. 60
IOUT (mA)
Min. 40
20
0 0 0.5 1 1.5 VOUT (V) 2 2.5 3
18
S17100JJ2V0DS
PD720133
3 4 Receiver Sensitivity for Transceiver at DP/DM
Level 1
+400 mV Differential
Point 3
Point 4
Point 1
Point 2
0V Differential
Point 5
Point 6
Level 2
-400 mV Differential
0%
Unit Interval
100%
3 5 Receiver Measurement Fixtures
Test Supply Voltage 15.8 USB Connector Nearest Device Vbus D+ DGnd 50 Coax 50 Coax + To 50 Inputs of a High Speed Differential Oscilloscope, or 50 Outputs of a High Speed Differential Data Generator -
15.8
143
143
MIN. CIN COUT CIO VDD = 0 V, TA = 25 fC = 1 MHz 0V 4 4 4
MAX. 6 6 6 pF pF pF
S17100JJ2V0DS
19
PD720133
1
MAX. VDD25 PENUM-BUS Un-configured state 55 25 PW-BUS 100 75 PW_SPD-BUS Suspend state 15 22 13 235 10 10 5 mA mA A 3 4 10 10 mA mA VDD33 AVDD25
2
MAX. VDD25 PENUM-SELF Un-configured state 90 60 PW-SELF 100 75 PW_SPD-SELF PW_UNP PW_COM IDE Suspend state Unplug state 50 50 50 25 13 500 500 500 10 10 15 15 15 mA mA A A A 5 5 10 10 mA mA VDD33 AVDD25
20
S17100JJ2V0DS
PD720133
AC VDD33 = 3.3 3.6 V, VDD25 = 2.3 2.7 V, TA = 0 70
MIN. fCLK 500 ppm 500 ppm tDUTY 45
TYP. 30 30 50
MAX. 500 ppm 500 ppm 55 MHz MHz %
1. 2.
100 ppm
MIN. trst 2
MAX.
s
USB (1/2)
MIN. Full-speed Source Electrical Characteristics Rise time (10% - 90%) Fall time (90% - 10%) Differential rise and fall time matching Full-speed data rate for device which are high-speed capable Frame interval Consecutive frame interval jitter Source jitter total (including frequency tolerance): To next transition For paired transitions Source jitter for differential transition to SE0 transition Receiver jitter: To next transition For paired transitions Source SE0 interval of EOP Receiver SE0 interval of EOP Width of SE0 interval during differential transition tJR1 tJR2 tFEOPT tFEOPR tFST -18.5 -9 160 82 14 +18.5 +9 175 ns ns ns ns ns tDJ1 tDJ2 tFDEOP -3.5 -4.0 -2 +3.5 +4.0 +5 ns ns ns tFRAME tRFI No clock adjustment 0.9995 1.0005 42 ms ns tFR tFF tFRFM tFDRATHS CL = 50 pF, RS = 36 CL = 50 pF, RS = 36 (tFR/tFF) Average bit rate 4 4 90 11.9940 20 20 111.11 12.0060 ns ns % Mbps MAX.
S17100JJ2V0DS
21
PD720133
(2/2)
MIN. High-speed Source Electrical Characteristics Rise time (10% - 90%) Fall time (90% - 10%) Driver waveform High-speed data rate Microframe interval Consecutive microframe interval difference tHSR tHSF 3-6 tHSDRAT tHSFRAM tHSRFI 479.760 124.9375 480.240 125.0625 4 high-spee d Data source jitter Receiver jitter tolerance Device Event Timings Time from internal power good to device pulling D+ beyond VIHZ (min.) (signaling attached) Debounce interval provided by USB system software after attach Inter-packet delay for full-speed tIPD 2 Bit times Inter-packet delay for device response w/detachable cable for full-speed High-speed detection start time from suspend Sample time for suspend vs reset Time to detect bus suspend state Power down under suspend Reversion high-speed Drive Chirp K width Finish Chirp K assertion Start sequencing Chirp K-J-K-J-K-J Finish sequencing Chirp K-J Detect sequencing Chirp K-J width Sample time for sequencing Chirp Reversion time to high-speed High-speed detection start time Reset completed time tCKO tFCA tSSC tFSC tCSI tSCS tRHA tHDS tDRS 2.5 10 -500 2.5 1 2.5 500 3000 1 7 100 -100 ms ms time from suspend to tCSR tSPD tSUS tRHS 100 3.000 875 3.125 10 1.333 tSCA 2.5 tRSPIPD1 6.5 Bit times tATTDB 100 ms tSIGATT 100 ms 3-6 3-4 Mbps 500 500 ps ps MAX.
s
Bit times
s s
ms ms
s
s s s
ms
s s
ms
22
S17100JJ2V0DS
PD720133
IDE
PIO
Mode 0 Cycle time (min.) Address setup time (min.) 16 bits DIOR/DIOW pulse width (min.) 8 bits DIOR/DIOW pulse width (min.) DIOR/DIOW recovery time (min.) DIOW data setup time (min.) DIOW data hold time (min.) DIOR data setup time (min.) DIOR data hold time (min.) DIOR 3-state delay time (max.) Address hold time (min.) IORDY read data valid time (min.) IORDY setup time (min.) IORDY pulse width (max.) IORDY inactive to Hi-Z time (max.) t2i t3 t4 t5 t6 t6Z t9 tRD tA tB tC t0 t1 t2 600 70 165 290 60 30 50 5 30 20 0 35 1250 5 Mode 1 383 50 125 290 45 20 35 5 30 15 0 35 1250 5 Mode 2 240 30 100 290 30 15 20 5 30 10 0 35 1250 5 Mode 3 180 30 80 80 70 30 10 20 5 30 10 0 35 1250 5 Mode 4 120 25 70 70 25 20 10 20 5 30 10 0 35 1250 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
IORDY
Mode 0 - 2
Mode 3 - 4
Multi Word DMA
Mode 0 Cycle time (min.) DIOR/DIOW pulse width (min.) DIOR data access time (max.) DIOR data hold time (min.) DIOR data setup time (min.) DIOW data setup time (min.) DIOW data hold time (min.) DMACK data setup time (min.) DMACK data hold time (min.) DIOR negate pulse width (min.) DIOW negate pulse width (min.) DIOR-DMARQ delay time (max.) DIOW-DMARQ delay time (max.) DMACK 3-state delay time (max.) CS setup time (min.) CS hold time (min.) t0 tD tE tF tGr tGw tH tI tJ tKr tKw tLr tLw tZ tM tN 480 215 150 5 100 100 20 0 20 50 215 120 40 20 50 15 Mode 1 150 80 60 5 30 30 15 0 5 50 50 40 40 25 30 10 Mode 2 120 70 50 5 20 20 10 0 5 25 25 35 35 25 25 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
S17100JJ2V0DS
23
PD720133
Ultra DMA
Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. Average cycle time for 2 cycles Minimum cycle time for 2 cycles Cycle time for 1 cycle Data setup time on receive side Data hold time on receive side Data setup time on transmit side Data hold time on transmit side First STROBE time Interlock time with limitation Minimum interlock time Interlock time without limitation Output release time Output delay time Output stabilization time (from release) Envelope time STROBE DMARDY delay time Last STROBE time Pause time IORDY pull-up time IORDY wait time DMACK setup/hold time STROBE STOP time t2CYC t2CYC tCYC tDS tDH tDVS tDVH tFS tLI tMLI tUI tAZ tZAH tZAD tENV tSR tRFS tRP tIORYZ tZIORY tACK tSS 240 235 114 15 5 70 6 0 0 20 0 20 0 20 160 0 20 50 230 150 10 70 50 75 20 160 156 75 10 5 48 6 0 0 20 0 20 0 20 125 0 20 50 200 150 10 70 30 60 20 120 117 55 7 5 34 6 0 0 20 0 20 0 20 100 0 20 50 170 150 10 70 20 50 20 90 86 39 7 5 20 6 0 0 20 0 20 0 20 100 0 20 50 130 100 10 55 NA 60 20 60 57 25 5 5 6 6 0 0 20 0 20 0 20 100 0 20 50 120 100 10 55 NA 60 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
24
S17100JJ2V0DS
PD720133
ROM
MIN. Clock frequency Clock pulse width low Clock pulse width high Clock low to data valid Start hold time Start setup time Data in hold time Data in setup time Data out hold time Stop setup time Time the bus must be free before a new transmission can start Write cycle time tWR 10 ms tSCL tLOW tHIGH tAA tHD.STA tSU.STA tHD.DAT tSU.DAT tDH tSU.STO tBUF 4.7 4.0 100 4.0 4.7 0 0.2 50 4.7 10 4500 MAX. 100 kHz
s s
ns
s s
ns
s
ns
s s
3 6 Transmit Waveform for Transceiver at DP/DM
Level 1
Point 3 Point 4
+400 mV Differential
Point 1
Point 2
0V Differential
Point 5
Point 6
Level 2 Unit Interval 0% 100%
-400 mV Differential
3 7 Transmitter Measurement Fixtures
Test Supply Voltage 15.8 USB Connector Nearest Device Vbus D+ DGnd 50 Coax 50 Coax + To 50 Inputs of a High Speed Differential Oscilloscope, or 50 Outputs of a High Speed Differential Data Generator -
15.8
143
143
S17100JJ2V0DS
25
PD720133
System reset timing
trst
RESETB
ROM ROM 5 0.1197 512 0.5678 ms 66.855 ms 8K 986.15 ms
ROM
USB power-on and connection events
Hub port power OK Hub port power-on VBUS VIH(min) VIH D+ or D-
Attatch detected
Reset recovery time
4.01 V
USB system software reads device speed
tSIGATT tATTDB
10 ms
USB differential data jitter for full-speed
tPERIOD Differential Data Lines Crossover Points
Consecutive Transitions N x tPERIOD + tDJ1 Paired Transitions N x tPERIOD + tDJ2
26
S17100JJ2V0DS
PD720133
USB differential-to-EOP transition skew and EOP width for full-speed
tPERIOD Differential Data Lines Crossover Point Crossover Point Extended
Diff. Data-toSE0 Skew N x tPERIOD + tFDEOP
Source EOP Width: tFEOPT Receiver EOP Width: tFEOPR
USB receiver jitter tolerance for full-speed
tPERIOD Differential Data Lines
tJR
tJR1
tJR2
Consecutive Transitions N x tPERIOD + tJR1 Paired Transitions N x tPERIOD + tJR2
USB connection sequence on full-speed system bus
Pull-up is active. USB bus FSJ tHDS tFCA tDRS T0 tSCA tCKO tSCS Chirp K device out Reversion to full-speed mode FSJ
USB connection sequence on high-speed system bus
Pull-up is active. Chirp K device out USB bus FSJ tHDS tFCA T0
tSCA
Chirp state from host/hub K J K J K J K
Reversion to high-speed mode J tRHA Reset Complete
tCKO
tSSC tCSI tSCS
tFSC
S17100JJ2V0DS
27
PD720133
USB reset sequence from suspend state on full-speed system bus
Pull-up is active. USB bus FSJ tSCA tFCA tDRS T0 tCKO tSCS
Chirp K device out FSJ
USB reset sequence from suspend state on high-speed system bus
Chrip state from host/hub K tSCA tFCA T0 tCKO tSSC tCSI J K J K J K J tRHA tSCS tFSC Reversion to high-speed mode Reset Complete
Pull-up is active. USB bus FSJ
Chirp K device out
USB suspend and resume on full-speed system bus
FS EOP USB bus tSPD tSUS
Power will be down
FSJ
FSK
FSJ
Note time required to relock PLL and stabilize oscillator.
USB suspend and resume on high-speed system bus
Reversion to full-speed mode
Reversion to high-speed mode
High-speed packet
High-speed packet
USB bus
tSPD
T0
FSJ
t tCSR tSUS
FSK
tRHS
Power will be down
Note time required to relock PLL and stabilize oscillator.
28
S17100JJ2V0DS
PD720133
IDE PIO mode timing
IDECS1B, IDECS0B IDEEA2-IDEEA0 IDEIORB IDEIOWB IDED15-IDED0 (WRITE) IDED15-IDED0 (READ)
H L H L H L
t1
t0 t2 t3
t9 t2i t4
t5 H L tA IDEIORDY H L tB tRD tC
t6Z t6
IDE multi word DMA mode timing
H L H L H L
tI tM tLr/tLw tD tGr tGw tF tH tKr/tKw
IDECS1B, IDECS0B
IDEDRQ IDEDAKB IDEIORB IDEIOWB IDED15-IDED0 (READ) IDED15-IDED0 (WRITE)
tN
t0
H L H L H L
tJ tZ
tE
IDE ultra DMA mode data-in timing
H L H L H L H L H L H L H L H L tAZ tACK tACK tUI tACK tACK tENV tENV tZIORY tDVS
Data
IDEDRQ IDEDAKB IDEIOWB (STOP) IDEIORDY (HDMARDY) IDEIORB (DSTROBE) IDED15-IDED0 IDECS1B, IDECS0B IDEA2-IDEA0
tSS tFS tZAD tFS tZAD t2CYC tCYC tDVH
Data
tLI
tLI tLI
tMLI
tACK tACK tIORYZ
tCYC
Data
tZAH tDVS tAZ
CRC
tDVH tACK tACK
S17100JJ2V0DS
29
PD720133
IDE ultra DMA mode data-in stop timing
H L H L tRP IDEIOWB (STOP) IDEIORB (HDMARDY) IDEIORDY (DSTROBE) IDED15-IDED0 H L H L H L H L tSR tRFS
IDEDRQ IDEDAKB
IDE ultra DMA mode data-in end timing
H L H L
IDEDRQ IDEDAKB IDEIOWB (STOP) IDEIORB (HDMARDY) IDEIORDY (DSTROBE) IDED15-IDED0 IDECS1B, IDECS0B IDEA2-IDEA0
tLI
tMLI
tACK
H L
tZAH tRP tAZ tLI tMLI tACK tIORYZ tDVS tDVH
CRC
H L H L H L H L
tRPS
tACK
IDE ultra DMA mode data-out timing
H L H L H L H L H L H L H L H L tZIORY tACK tDVS
Data
IDEDRQ IDEDAKB IDEIOWB (STOP) IDEIORDY (DDMARDY) IDEIORB (HSTROBE) IDED15-IDED0 IDECS1B, IDECS0B IDEA2-IDEA0
tUI tACK tENV tLI tUI tRFS t2CYC tCYC tDVH
Data
tRP tMLI tACK tIORYZ tLI tCYC
Data
tLI
tMLI tDVS
CRC
tACK tDVH tACK tACK
tACK tACK
30
S17100JJ2V0DS
PD720133
IDE ultra DMA mode data-out stop timing
H L H L H L H L H L H L
IDEDRQ IDEDAKB IDEIOWB (STOP) IDEIORB (HDMARDY) IDEIORDY (DSTROBE) IDED15-IDED0
tRP
tSR tRFS
IDE ultra DMA mode data-out end timing
H L H L H L tSS H L H L H L H L tACK tDVS tDVH
CRC
IDEDRQ IDEDAKB IDEIOWB (STOP) IDEIORB (HDMARDY) IDEIORDY (DSTROBE) IDED15-IDED0 IDECS1B, IDECS0B IDEA2-IDEA0
tLI tLI
tMLI
tACK tIORYZ
tLI
tACK
IDE ultra DMA mode data skew timing
t2CYC IDEIORB (Output side) H L tDVS H IDED15-IDED0 L (Output side) Delay, skew, etc., by cable IDEIORDY (Input side) IDED15-IDED0 (Input side) H L H L Output side Input side xSTROBE DD0 : : DD15
Data
tCYC tDVH
Data
tCYC
Data
tDS
tDH
S17100JJ2V0DS
31
PD720133
Serial ROM access timing
tHIGH tLOW SCL tSU.STA SDA (Output) tAA SDA (Input) tDH tBUF tHD.STA tHD.DAT tSU.DAT tSU.STO tLOW
Serial ROM write cycle timing
PIO1
PIO0 Word n
8th bit
ACK
tWR Stop condition Start condition
32
S17100JJ2V0DS
PD720133
4.
PD720133GB-YEU-A PD720133GB-YEU-Y
12.00.2 10.00.2
48 49
33 32 1.10.1 1.0
10.0 0.2 12.00.2
0.25
3+4 -3 64 1 1.25 1.25 0.22 0.05 0.08 0.5
M
0.5 0.60.15
17 16
0.10.05
1.00.2 S
0.08 S
0.17 +0.03 -0.07
S64GB-50-YEU-1
S17100JJ2V0DS
33
PD720133
5.
http://www.necel.com/pkg/ja/jissou/index.html
51
* PD720133GB-YEU-A / PD720133GB-YEU-Y 64
260 10 220 60 60 160 180 3 3 < > 125 120
TQFP
10 10
IR60-103-3
10
300
3
25
65 (RH)
34
S17100JJ2V0DS
PD720133
S17100JJ2V0DS
35
PD720133
EEPROM
NEC
* * *
2004 6
*
*
*
OA
AV
NEC
NEC
M8E
02.11
044(435)5111
http://www.necel.co.jp/
044-435-9494 E-mail info@necel.com
C04.2T

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